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-- Company: 
-- Engineer: 
-- 
-- Create Date:    09:46:38 12/03/2014 
-- Design Name: 
-- Module Name:    id_ex - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity id_ex is
	port(
		clk,branch_conflict:in std_logic;
		wb_in,wm_in:in std_logic;
		alu_in:in std_logic_vector(3 downto 0);
		data1_in,data2_in,imm_in:in std_logic_vector(15 downto 0);
		rd_in,rs1_in,rs2_in:in std_logic_vector(3 downto 0);
		rm_in,pcen_in,immen_in:in std_logic;
		nextpc_in:in std_logic_vector(15 downto 0);
		instruction_in:in std_logic_vector(15 downto 0);
		wb_out,wm_out:out std_logic;
		alu_out:out std_logic_vector(3 downto 0);
		data1_out,data2_out,imm_out:out std_logic_vector(15 downto 0);
		rd_out,rs1_out,rs2_out:out std_logic_vector(3 downto 0);
		rm_out,pcen_out,immen_out:out std_logic;
		nextpc_out:out std_logic_vector(15 downto 0);
		instruction_out:out std_logic_vector(15 downto 0)
	);
end id_ex;

architecture Behavioral of id_ex is

begin
	process(clk)
	begin
		if clk'event and clk='1' then
			if branch_conflict='0' then
				wb_out<=wb_in;
				wm_out<=wm_in;
				alu_out(3 downto 0)<=alu_in(3 downto 0);
				data1_out(15 downto 0)<=data1_in(15 downto 0);
				data2_out(15 downto 0)<=data2_in(15 downto 0);
				imm_out(15 downto 0)<=imm_in(15 downto 0);
				rd_out(3 downto 0)<=rd_in(3 downto 0);
				rs1_out(3 downto 0)<=rs1_in(3 downto 0);
				rs2_out(3 downto 0)<=rs2_in(3 downto 0);
				rm_out<=rm_in;
				pcen_out<=pcen_in;
				immen_out<=immen_in;
				nextpc_out(15 downto 0)<=nextpc_in(15 downto 0);
				instruction_out(15 downto 0)<=instruction_in(15 downto 0);
			else
				wb_out<='0';
				wm_out<='0';
				alu_out(3 downto 0)<="0000";
				data1_out(15 downto 0)<="0000000000000000";
				data2_out(15 downto 0)<="0000000000000000";
				imm_out(15 downto 0)<="0000000000000000";
				rd_out(3 downto 0)<="0000";
				rs1_out(3 downto 0)<="0000";
				rs2_out(3 downto 0)<="0000";
				rm_out<='0';
				pcen_out<='0';
				immen_out<='0';
				nextpc_out(15 downto 0)<="0000000000000000";
				instruction_out(15 downto 0)<="0000000000000000";
			end if;
		end if;
	end process;

end Behavioral;

